Overshoot reduction in VCO calibration for serial link phase lock loop (PLL)

ABSTRACT

A circuit design, method, and system for tracking VCO calibration without requiring an over-designed divider as in conventional implementation. A filter reset component is added to the inputs of the VCO. A process step is added to the calibration mechanism/process that shorts the filter nodes and thus centers the frequency of the VCO before stepping from one frequency band to the next.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates generally to electronic circuits and inparticular to phase locked loop (PLL) circuits. Still more particularly,the present invention relates to calibration of the PLL circuits.

2. Description of the Related Art

Voltage controlled oscillator (VCO) calibration algorithm is utilized inthe 6 Gbps harmonic oscillator for high speed serial (HSS) links.However, in electronic circuits and particularly phase locked loop (PLL)circuits, VCO calibration causes frequency overshoot. Most conventionalapproaches to VCO calibration do not adjust for Overshoot, which is acondition that frequently occurs during the calibration.

FIGS. 1, 3, 5, and 7 are example graphs illustrating the application ofthe prior art calibration algorithm to a PLL circuit. Each graph tracksthe voltage (+ or − from a 0 voltage, central reference point) along thebottom X axis and the frequency band (relative to the voltage) along theright most vertical edge (Y axis). Six points of reference are shownwithin the graph of FIG. 1, one associated to frequency zero (F0), twoassociated with frequency one (F1), and three associated with frequencytwo (F2). Three of the points of reference are indicated with theselected frequency band assigned/selected.

In conventional designs of circuits that utilize VCO calibration,frequency overshoot caused by VCO calibration is tracked by dividercircuitry to prevent erroneous lock conditions in the circuit. Theseconventional circuits require the divider be over-designed (i.e., builtto require more power and area) in order to track the VCO. However,given the ever-present desire for smaller and lower power consumingcircuits, the use of such over-designed dividers provided for correctVCO calibration is a less-than desirable fix to the problem ofovershoot.

SUMMARY OF THE INVENTION

Disclosed is a circuit design, method, and system for tracking voltagecontrolled oscillator (VCO) calibration without requiring anover-designed divider as in conventional implementation. A filter resetcomponent is added to the inputs of the VCO. A process step is added tothe calibration mechanism/process that shorts the filter nodes and thuscenters the frequency of the VCO before stepping from one frequency bandto the next.

The above as well as additional objectives, features, and advantages ofthe present invention will become apparent in the following detailedwritten description.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention itself, as well as a preferred mode of use, furtherobjects, and advantages thereof, will best be understood by reference tothe following detailed description of an illustrative embodiment whenread in conjunction with the accompanying drawings, wherein:

FIG. 1 is a graph matching frequencies to frequency bands plottedagainst required differential voltage during VCO calibration;

FIG. 2 is an example of the PLL with VCO calibration circuit, enhancedwith a divide-by-M component and filter reset component according to oneembodiment of the invention;

FIGS. 3, 5, and 7 illustrate frequency overshoot during VCO calibrationaccording to conventional implementation;

FIGS. 4, 6 and 8 illustrate corrections to the frequencyovershoot/undershoot conditions of FIGS. 3, 5 and 7, respectively,during VCO calibration utilizing the method/mechanisms described withinembodiments of the invention; and

FIG. 9 is a flow chart illustrating the process by which corrections toVCO calibration is completed utilizing the enhanced methods/mechanismsprovided by one embodiment of the invention.

DETAILED DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT

The present invention provides a circuit design and method for reducingovershoot in voltage controlled oscillator (VCO) calibration for highspeed serial (HSS) link phase locked loop (PLL) circuits. A filter resetcomponent is added to the inputs of the VCO. A step is added to thecalibration process/mechanism that shorts the filter nodes and thuscenters the frequency of the VCO before stepping from one frequency bandto another. The added step reduces the requirements for the divider,which is then designed as a smaller and lower power consuming device.

Referring now to the figures, and in particular FIG. 2, which provides ablock diagram of a circuit designed with enhanced mechanisms forcorrecting frequency overshoot caused by VCO calibration withoutrequiring an over-designed divider circuit. Specifically, the circuitillustrated represents a frequency multiplier phase locked loop (PLL).Unlike conventional implementations, the illustrated circuit of FIG. 2comprises a filter reset (shorting) component/function 220.Additionally, the circuit 200 includes a redesigned divide-by-N(divider) 214, which is a smaller area and consumes measurably lesspower than conventional dividers utilized in similar circuits. Further,circuit 200 comprises a differential loop filter with positive voltagecontrolled branch (VCP) 214 and negative voltage controlled branch (VCN)214.

The filter reset component 220 provides a mechanism for resetting theVCO frequency to the center point by shorting the two sides of the loopfilter together. This resetting of the VCO frequency to the center pointassures that the VCO frequency does not exceed the capability of thefeedback divider 214, thus enabling the smaller and less power-consumingdesign of the feedback divider 214. In the illustrative embodiment, thereset component 220 comprises a transistor, which is coupled at the gateand source terminals to positive and negative inputs of VCO 210. Eachtime a band is selected, the gate of the transistor is taken to a highvoltage (which shorts the transistor's sides together to a commonvoltage) and this operation resets the PLL to a known frequency.

During calibration, input frequency (Fin) 202 is passed through (and/orinfluenced by) a sequence of circuit components, namely phase frequencydetector (PFD) 204, charge pump (CP)/low pass filter (LPF) 206,differential loop filter (214,216), then VCO 210 to produce an outputfrequency (Fout) 212. Additionally, output from VCO 210 is providedthrough feedback loop 215, which includes divide-by-N (divider) 214. Theoutput of divider 214 is fed as a second input into PFD 204. Asillustrated, each branch of differential loop filter (214,216) comprisesa resistor and two capacitors, utilized to hold the respective lower orupper charge generated by charge pump 206. The magnitude of the voltagevalues between VCP and VCN determines the frequency of VCO 210. Withthis configuration, the present circuit 200 accurately tracks the VCO210, while consuming less power, requiring less area on the chip/circuitboard, and prevents erroneous lock conditions.

According to the described embodiment, calibration is utilized to centera VCO's operating range for optimal performance (e.g., lowest jitter)and maximum tracking for temperature changes and hot-E effects. Thecalibration algorithm involves the VCO operating in frequency bands. Asthe bands increase, the frequency increases. The bands are steppedthrough in increasing order to find the band that requires the leastamount of differential voltage offset for the particular frequency. Eachtime a band is selected, the smallest selection window is applied, andthe differential control voltage is examined to see if the voltage fallswithin this window. If none of the bands within the selection windowsatisfies the criteria, then the selection window is increased and thebands are stepped through again. Accordingly, this process selects theband that best centers the differential control voltage.

FIG. 9 is a flow chart of the process by which overshoot in VCOcalibration is substantially reduced utilizing the circuit configurationand methods/techniques of the present invention, in accordance with oneembodiment. The process begins at block 902 which depicts the resettingof the circuit to a base frequency. During this reset, triggered whenparameter value RESET=1, the VRSEL (i.e., the sample window select bits)are set to 000 and the BANDSEL (the present frequency band, which iscontrolled by an eight bit parameter) is reset 00000000. Then, as shownat block 904, the sampling process is suspended for a preset period oftime (illustrated as 50 microseconds) to enable the circuit frequency toreturn to the center point. A new sample of the differential controlvoltage versus the VR sampling window and frequency lock is initiated,as shown at block 906. This also forces the filter reset.

Following, a decision is made at block 908 whether the frequency lock isokay and the control voltage is centered. If these two conditions aresatisfied, then the coarse calibration of the device is completed, asshown at block 910. Otherwise, the value of the BANDSEL is checked atblock 914 to determine if the value is less than the maximum frequencyvalue. If the value is less than the maximum value, then the BANDSELvalue is incremented at block 920. Then the process is made to waitanother time period (shown as 50 microseconds in the illustrativeembodiment) at block 924. The filter is then forced to reset at block912 and the process returned to block 904 at which the preset waitperiod occurs.

Returning to block 914, if the BANDSEL is not less than the maximum,then a next check is made at block 916 whether the VRSEL equals 111,which is the maximum width. If the VRSEL value equals 111, then acalibration error is recorded as shown at block 918. Otherwise, theVRSEL value is incremented and the BANDSEL value reset to 00000000, asindicated at block 922.

With the above process, the frequency provided to the feedback divider214 is slow enough to enable the divided to correctly divide thefrequency, thus preventing the divider from being stuck in an errorstate. The divider 214 is designed to be able to handle the center pointfrequency and is thus able to follow the changes in frequency bandssince the changes always begin at the “safe” center point. The inventionthus implements a scheme/circuit design that provides an organizedmethod of stepping up the VCO band frequency, while preventing the PLLfrom outrunning the speed capabilities of the divider utilizing theabove described control algorithm.

Referring now to FIGS. 3, wherein is illustrated the conventionalmethods of stepping through frequency bands during conventional VCOcalibration. As shown by FIG. 3, frequency F0 was achieved on Band5 witha significantly positive differential control voltage (i.e., at thepoint of overlap with Band5). When the band is stepped up to Band6 (toadjust for/reduce the positive differential control voltage required),the VCO overshoots the desired frequency for some time before the phaselocked loop is able to correct the overshoot. Thus one visibledisadvantage of this conventional method is that when the bands arestepped up the frequency may overshoot significantly. Consequently also,divider may not be able to operate correctly at this higher frequencyand may produce an irregular signal, which would cause the loop to lockat an incorrect frequency.

Recognizing the above problems with the conventional implementation, oneembodiment of the invention provides a solution to the overshoot problemdescribed above. Accordingly, as shown by the graph of FIG. 4, themethods/mechanism of the invention involves adding a step to thecalibration algorithm that centers the control voltages between bandsteps (i.e., band5 and band6 in the illustrative embodiment). Centeringthe control voltages between band steps controls the maximum frequencythat will be seen by the divider. In one embodiment, this centering isimplemented by shorting the two sides of the differential filter withthe transistor.

FIGS. 5 and 6 illustrate the application of the methods/mechanisms ofthe invention to a slightly lower frequency F0, for which calibrationovershoot is corrected to a slightly negative differential controlvoltage. FIG. 5 provides the conventional approach illustrating theovershoot to the next band (band6). As illustrated by the graph of FIG.6, obtained by shorting the two sides of the differential filter, theVCO calibration overshoot is corrected so that there is substantiallyless overshoot. In this embodiment also, the overshoot is defined as thecenter frequency of the top band.

FIGS. 7 and 8 illustrate the application of the methods/mechanisms ofthe invention to a slightly higher frequency F0, for which calibrationovershoot is corrected to a slightly positive differential controlvoltage. FIG. 7 provides the conventional approach illustrating theovershoot to the next band (band6). As illustrated by the graph of FIG.8, obtained by shorting the two sides of the differential filter, theVCO calibration overshoot is corrected so that there is actually aslight undershoot (indicated by the delta between the 0 voltage axes andthe point of intersection by F0 with Band6). In this embodiment also,the “overshoot” is defined as the center frequency of the top band.

While the invention has been particularly shown and described withreference to a preferred embodiment, it will be understood by thoseskilled in the art that various changes in form and detail may be madetherein without departing from the spirit and scope of the invention.

1. In a phase lock loop (PLL) circuit device, a method comprising:monitoring when a new frequency band is being selected to providevoltage controlled oscillator (VCO) calibration of the device; centeringthe current frequency of the VCO to a pre-established center point priorto stepping to the new frequency band; and stepping up to the newfrequency band only after the VCO frequency is centered at the centerpoint; wherein a divider within a feedback loop of the device processesfrequencies that are within a pre-determined range during the steppingup to the new frequency band.
 2. The method of claim 1, wherein saidcentering comprises shorting a differential loop filter with positiveand negative branches coupled to inputs of the VCO.
 3. The method ofclaim 2, wherein said shorting comprises applying a high voltage inputto the gate of a transistor configured with the source and drainrespectively coupled to either inputs of the VCO and to respective onesof positive and negative branches of the filter node.
 4. The method ofclaim 1, further comprising: sequentially stepping through each higherfrequency band of a plurality of sequentially-higher frequency bands byfirst centering the current frequency to the center point; wherein saidsequentially stepping is completed until the band that requires a leastamount of differential voltage offset is found for the particularfrequency.
 5. The method of claim 1, further comprising: selecting asmallest selection window to apply to the frequency band; determining isthe differential control voltage falls within the selection window; andincreasing the selection window and initiating a next sequentialstepping process when none of the bands within the current selectionwindow satisfies a pre-set criterion.
 6. The method of claim 5, furthercomprising: reporting an error in calibration when the final band of theplurality of bands is selected and the size of the selection window is amaximum width without the differential control voltage falling withinthe selection window.
 7. An electronic circuit device comprising: avoltage controlled oscillator (VCO); a charge pump coupled to the inputof the VCO; a differential loop filter with respectively positive andnegative branches coupled to a positive and a negative input of the VCO;a divider that receives an output from the VCO and which samples thefrequency of the VCO output signal; and means for calibrating the VCO,said means comprising means for centering the frequency of the VCO,wherein said frequency is automatically centered prior to stepping to anext sequential band during the calibrating.
 8. The device of claim 7,wherein said means for centering the frequency of the VCO furthercomprises: a filter reset transistor respectively coupled at its sourceand drain terminals to the input terminals of the VCO; and means forshorting the sides of the pair of differential loop filter together byturning on the filter rest transistor, wherein said shorting results inthe frequency of the VCO returning to a pre-established center-point. 9.The device of claim 7, wherein said divider is a divide-by-N circuit,where N is an integer selected to enable the divider to correctly dividethe frequency generated by the signal propagating through the VCOfeedback path.
 10. The device of claim 7, wherein the branches of thedifferential loop filter comprises a resistor and at least onecapacitor, which holds a charge generated on an output line of thecharge pump to which the filter branch is coupled.
 11. The device ofclaim 7, further comprising means for: monitoring when a new frequencyband is being selected to provide voltage controlled oscillator (VCO)calibration of the device; centering the current frequency of the VCO toa pre-established center point prior to stepping to the new frequencyband; and stepping up to the new frequency band only after the VCOfrequency is centered at the center point; wherein a divider within afeedback loop of the device processes frequencies that are within apre-determined range during the stepping up to the new frequency band.12. The device of claim 11, wherein said means for centering comprisesmeans for shorting a differential loop filter with positive and negativebranches coupled to inputs of the VCO.
 13. The device of claim 12,wherein said means for shorting comprises means for applying a highvoltage input to the gate of a transistor configured with the source anddrain respectively coupled to either inputs of the VCO and to respectiveones of positive and negative branches of the filter node.
 14. Thedevice of claim 1 1, further comprising means for: sequentially steppingthrough each higher frequency band of a plurality of sequentially-higherfrequency bands by first centering the current frequency to the centerpoint; wherein said sequentially stepping is completed until the bandthat requires a least amount of differential voltage offset is found forthe particular frequency.
 15. The device of claim 11, further comprisingmeans for: selecting a smallest selection window to apply to thefrequency band; determining is the differential control voltage fallswithin the selection window; and increasing the selection window andinitiating a next sequential stepping process when none of the bandswithin the current selection window satisfies a pre-set criterion. 16.The device of claim 14, further comprising means for: reporting an errorin calibration when the final band of the plurality of bands is selectedand the size of the selection window is a maximum width without thedifferential control voltage falling within the selection window.
 17. AVCO calibration circuit comprising the components of claim
 7. 18. Afrequency multiplier phase locked loop (PLL) comprising the componentsof claim
 7. 19. A computer system comprising a phase locked loop (PLL)device configured according to claim 7.